memdanceA new chapter in chip design.
We’re building AI-first infrastructure for chip design, verification, and post-silicon validation—so intelligent agents can carry out the engineering work, from implementation to investigation and checked results.
The designs we share put that infrastructure to work. Our focus is the tools and technology that let agents understand hardware, make changes, and evaluate the evidence.
The goal is not simply to make existing hardware tools faster with AI.
It is to rethink how hardware is built when AI becomes a first-class engineer.
We’re an early-stage startup. Our products are in heavy development. Here, we share what we’re thinking, learning, and building.
FROM THE JOURNAL
Notes from the workbench.
PinnedOur Ambition: Rethinking Chip Design Cycle with AI
Building AI-first hardware engineering infrastructure for more rigorous decisions, connected evidence, and earlier investigation of costly mistakes.
Why AI Hardware Engineering Needs Precise Unknowns
A missing 1, the difference between X and Z, and why an AI agent needs to know what its simulation result means.
Pause. Power Off. Resume the Same Experiment.
A checkpointed Dancer run on Orchestra: resume execution after power-off and verify the completed result.
One SoC, Multiple Engines, Matching Results
Taking a multicore workload through Dancer and checking its result and waveform streams across execution environments.
Evidence Built Into the Engineering Loop
How observed concurrency, event history, and meaningful execution checks turn results into better engineering decisions.
From Architecture to a Running Multicore SoC
An AI-operated workflow built on Memdance’s design, execution, and verification infrastructure.
When the Right Fix Is No Fix
A blinded debugging pilot: repair a hidden defect, reject a bad expectation, and leave an unsupported physical claim unresolved.
The Clocks Looked Identical. They Belonged to Different Domains.
Identical clock schedules, an invalid connection, and a constrained correction that preserves the valid neighbor.
The Formula Was the Same. The Numeric Semantics Were Not.
A low-precision dot product, four candidate repairs, and a signed-zero error in the reference oracle.
The Response Was Correct. The Transaction Was Wrong.
Tag reuse, reset, and transaction ownership: a controlled experiment in preserved history and bounded verification evidence.
Tracing a Hardware Failure to Evidence
An independent model, a controlled correction, and a result with clear boundaries.
Building a Chip Validation Stack from the Ground Up
An Arm validation stack for controlled execution, architectural checks, stress workloads, and precisely scoped results.